1. Field of the Invention
The invention relates to design of semiconductor chips. More specifically, the invention relates to a method and an apparatus for generating a plan for a power supply network to be added to a design of an integrated circuit.
2. Related Art
A power supply network for an integrated circuit (IC) design can be created in any of a number of different ways known in the prior art. U.S. Pat. No. 4,811,237 granted to Putatunda et al. on Mar. 7, 1989 entitled “Structured Design Method For Generation A Mesh Power Bus Structure In High Density Layout Of VLSI Chips” is incorporated by reference herein in its entirety. This patent describes an automated layout of a power bus distribution network.
U.S. Pat. No. 6,446,245 granted to Xing et al. on Sep. 3, 2002 and entitled “Method and Apparatus for performing power routing in ASIC design” is incorporated by reference herein in its entirety. This patent states that traditionally power routing is performed during the floor planning stage, before cell placement, and for this reason the location of the standard cells and hence the power consumption behavior is not known at the power routing stage. Also this design flow creates obstacles for cell placement optimization. Therefore, this patent describes a method in which standard cells are placed in the physical layout prior to power routing, and they are placed in a bottom-up hierarchical manner.